The GPFC architecture is designed to be scalable. Its basic configuration is a single board one, and it is a fully functional device. However, when more resources or new features are needed, extension boards can be added.
Herein, a single board configuration is primarily described. For multiboard configuration details see "Advanced features" and "Architecture" sections.
The GPFC is based on the Motorola's MCF5206 (ColdFire) RISC CPU chip, designed for low power and low cost embedded applications. The ColdFire family is a recently emerged successor for the well known M68k family.
The MCF5206 has a good performance (17 MIPS at 33MHz), large 4 GB address space and 32-bit data path. It incorporates on-chip an external bus controller, DRAM controller and several peripherals. The programming model looks very similar to the M68k one.
The GPFC design provides two options for the CPU clock frequency, 16 or 32 MHz. The minimal access time on the GPFC system bus is, accordingly, 60 or 30 ns (in the burst mode). A single word (non bursting) fastest access takes 120 or 60 ns.
The bus operation is programmable via the CPU bus controller, which maps the entire 4 GB address space on several "windows". Each window represents a memory pool or peripheral. Window access is individually pre-programmed for bus cycle duration and data path width (32/16/8 bit). Maximum window size is 256 MB, but some GFPC configurations may limit it to 64 MB. As many as eight windows are supported, and the basic GPFC configuration uses two of them.
The DRAM controller provides two more windows (banks), but with a specific DRAM access protocol. From these the basic GPFC configuration uses one bank for the 2 or 4 MB basic RAM pool.
The most important GPFC's I/O resource is the IndustryPack (IP) interface. It is implemented in Xilinx FPGA chip (see more in the "Architecture" section). The GPFC's IP controller can support maximum four IP modules, but a single board GPFC configuration provides only two IP "slots" (two single size IP modules or one double size module). Yet two IP slots can be provided with an extension board.
The GPFC currently implements reduced IP specification (VITA-4, 1995): 8 MHz clock and 16 bit data path are only supported and DMA mode is not supported. This seems to be adequate for the most of foreseen applications while keeps simple the board design.
The IP-module's connection to the external world is provided via the onboard 50-pin header, following the style of the most of commercially available IP carriers. Thus, all IP-module's accessories (flat cable assemblies, transition submodules, etc.) can be used with the GPFC without modifications.
The GPFC main board also is equipped with several "directly attached" I/O peripherals. Some of them actually are the MCF5206 on-chip peripherals while others were added in the GPFC design:
The MCF5206 CPU chip contains two high speed programmable UARTs. Both UART channels are routed to the onboard auxiliary connector for application dependent usage.
The first UART channel is optionally supplied with the onboard RS232 driver and a separate connector to enable the direct terminal or host connection. The RS232 driver can be dynamically disconnected (shutdown) if application uses the UART channel in a different way, or for the power saving purpose.
Both timers are the MCF5206 onchip peripherals, which can be configured for different operation modes under the program control.
Again, the MCF5206 onchip peripheral. This port can be programmed pin by pin, either for input or output. It is routed to the auxiliary onboard connector.
This port has been added in the GPFC design to provide the reading a programmable (external) switch at system startup. However, it can be used for other application dependent purpose. The port is routed to a separate auxuliary connector.
The GPFC main board provides four interrupt inputs which can be connected to arbitrary external signal sources or used with extension boards. One more interrupt input is intended for use with the (external) ABORT button. All these inputs are routed to the auxiliary onboard connector.
The GPFC offers a flexible interrupt processing scheme. All interrupts (except ones originated from the CPU internal peripherals) are processed in the central interrupt controller (see the "Architecture" section for more details).
The controller supports as many as 13 interrupt sources, including 8 IP-interrupts, ABORT interrupt and 4 "external" interrupts. The latter can come either from extension boards, or from the auxiliary connector located on the main board.
Each interrupt can be individually configured for priority and interrupt vector. This allows to properly balance the system interrupt load and also to avoid vector conflicts when one makes use of some poorly designed IP modules.
The GPFC has two ROM pools onboard: EPROM/FLASH and SEEPROM. The first one is used for fetching the code to be executed at system startup and the second one can be used by applications for non-volatile data storage.
The EPROM/FLASH pool is provided via a single 32-pin socket
which can accept a chip from the following list:
- EPROM: 256 KB, 512 KB, 1 MB.
- FLASH: 128 KB, 256 KB, 512 KB.
The SEEPROM pool is provided by the two soldered 8 KB chips. It is accessed via I2C serial bus interface (the CPU onchip peripheral).
FLASH and SEEPROM can be written onboard in the run time.
The MCF5206 CPU has a watchdog timer feature, which can be enabled and configured during the system startup. When this feature enabled, the software must periodically reset the watchdog timer to confirm that everything is allright. If not reset in time, the watchdog timer forces the CPU reset, thus making the system to restart. The watchdog timer can be configured for period duration and for alarm action (reset or non-masked interrupt).
Another watchdog is hidden in the onboard power monitor chip. It continuously watches the supply voltage level and generates the system reset when the voltage is low (brown-up reset feature is supported too).
The GPFC has been specifically designed for low power applications. The goal was to provide the exploiting GPFC without the forced air cooling. Many features contribute to the low power consumption and effective heat dissipation (see the "Architecture" section for details). However, the final decision on avoiding the forced air cooling depends on IP modules installed. Also, the overall environment and the GPFC board space orientation have to be taken into account.
The GPFC board design facilitates embedding the board into the controlled equipment. See the "Architecture" section for details and "Applications" section for example of embedded application.
Alternatively, the GPFC board can be mounted in a separate box, containing also a control panel, I/O connectors and power supply. One such standalone configuration is currently under design.