Architecture and implementation details
The whole GPFC functionality is based on the system kernel,
which includes the following key components:
- The ColdFire MCF5206 CPU
- The multifunctional system controller
- The system bus
- The IP bus
- The basic RAM pool
- The basic PROM pool
- The clock/reset/power_management logic
The system kernel is implemented on the GPFC's main board.
This basic configuration, although fully functional,
can be further extended with additional resources and new features
using stackable extension boards
(see here for a figure).
The MCF5206 CPU chip is designed for compact, low cost and low power embedded
applications.
Besides a CPU unit, the chip contains several devices facilitating
the overall system design to be simpler, cheaper and
less power/space consuming:
The external bus controller and DRAM controller
First, the external bus controller and DRAM controller provide
the mostly glueless interfacing for memories and peripherals to
the (external) CPU bus.
The CPU accesses the external bus via ports, called
"chip selects" ("banks" in the DRAM controller).
These ports map the entire 4 GB address space on a number of "windows".
Each port is individually programmable for
window base address and size (max 256 MB) and data path width (32/16/8-bit).
When the window is accessed, the port generates an individual "chip select"
signal to select an appropriate peripheral (RAS signal for DRAM bank).
Thus, the external bus address space is effectively multiplied
by the number of available ports, using this mechanism.
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Note:
The CPU chip shares 4 pins for either address lines or
chip select signals. These pins are: cs4/A24-cs7/A27.
That is, system designer has to choose between the number of
available chip select ports and address space size.
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The port's bus cycle parameters are also programmable, allowing
a number of different modes of operation to be implemented.
Port can be programmed for either a single word access or
burst access, and for different cycle duration and termination options.
In the GPFC design, the main board makes use of the two chip select ports
(cs0, cs1) and one DRAM port (bank_1).
The two more chip select ports (cs4, cs5) are excluded from the use to provide
the 64 MB address space - see the note about the shared CPU pins above.
Remaining ports (cs2, cs3, cs6, cs7, DRAM bank_2) are free for extensions.
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Note:
A specific extension board design may use cs6/A26 and cs7/A27 lines
for further extending the address space at the cost of decreasing the
number of available chip select ports.
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The on-chip peripherals
Second, several on-chip peripherals provide functions needed in the
most of designs. These are: 2 timers, 2 UARTs, 8-bit parallel I/O port
with individual pin programming for input or output, fast 512 bytes SRAM
pool and I2C serial bus interface.
All on-chip peripherals are either used in the GPFC design
or made available for use with GPFC applications:
I2C serial bus interface provides the SEEPROM pool connection,
UARTs and 8-bit I/O port are routed to the onboard auxiliary connectors.
(SRAM and timers do not need external circuitry).
Performance aspects
The MCF5206 may run with any clock frequency in the range [0-max].
There are three chip modifications available,
supporting 16/25/33 MHz max clock frequencies.
The GPFC can use any of the two clocks, 16 or 32 MHz,
and, accordingly, the two chip modifications from the above mentioned.
The shortest external bus cycle to access a single word
requires 2 clock periods,
and only 1 period in the busrt mode, when accessing a sequence of words.
That means, the 32 MHz GPFC version can access a 32-bit word
in about 30 ns, when runs in the busrt mode.
The GPFC's main board currently has no peripherals able
to run so fast (the fastest one, DRAM, provides 60 ns access time).
However, this performance potential is open for use with extension boards.
The MCF5206 has a decoupled pipelined mechanism for instruction
fetch/execution and onchip instruction cache.
Both these features considerably improve the CPU performance.
Low power features
The intrinsically low power consumption of the MCF5206 can be further reduced
by proper programming of its internal devices.
Many of them have programmable power saving features, allowing
dynamically change the device state under the program control.
Warning:
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Herein, we described the MCF5206 in a very
simplified manner.
We hope this sketch is sufficient to understand the
GPFC archtecture, but it is definitely incomplete
for any other purpose.
We recommend you to read the
MCF5206 user's manual
for exact and complete information.
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The GPFC system bus is primarily derived from the MCF5206 CPU
external bus, but with some limitations and extensions.
The basic bus features are:
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26 address lines provide a 64 MB address space
for each "chip_select" or DRAM bank port.
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32 data lines provide 32/16/8-bit data transfers.
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6 "chip_select" ports and 2 DRAM bank ports are available for
accessing memory and peripherals (external to the CPU).
The main GPFC board uses DRAM bank_1 and the two chip_select ports
(cs0, cs1).
Remaining ports (cs2, cs3, cs6, cs7, DRAM bank_2)
are free for extensions
(see the note above).
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Address, data and control lines are powered with
bus transceivers. They work in the "bus hold" mode
to minimize bus noise levels and
maintain CMOS signal levels to minimize the system's
power consumption (see the
"Low power features"
section for details).
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All system bus signals are routed to the interboard (extension)
connector.
These signals can be directly used to interface additional
CMOS memories and/or peripherals.
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The bus runs in a single master mode, so that the CPU is
the only bus master.
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The original CPU bus is extended with:
- clock signals
- interrupt request signals
- IP control signals
All these are available on the interboard (extension) connector.
The main GPFC board contains basic RAM and PROM pools.
This enable the board to be a fully functional computer.
Extension boards can significantly add to these basic pools,
providing the system with larger and faster memory resources.
The basic RAM pool is implemented with two soldered DRAM chips
(TMS418160 type)
and is accessed via the DRAM bank_1 port.
The pool is organized sequentially, thus allowing to use
only one chip for the minimal configuration
(this, however, limits the port width to 16 bit).
Each chip provides the 2 MB space (1M x 16), so the total pool size
is 4 MB.
The basic RAM pool can be extended with additional DRAM memory
(located on extension boards). The two options are available:
- using the DRAM bank_2 port (any port width)
- using the free space in the DRAM bank_1 port (16-bit port width).
Another way for memory extension is to make use of
free chip_select ports available in the CPU bus controller
(SRAM chips can be directly interfaced to the system bus,
while DRAM will require an address multiplexing logic).
The basic PROM pool is implemented with
a single (socket installable) EPROM or FLASH chip.
The pool is accessed via the chip_select port 0,
which is used by the CPU to fetch the initial code on powerup.
Port's data width is 8 bit.
The following industry standard chips can be installed into the socket:
| EPROM |
FLASH |
256 KB (27C2001)
512 KB (27C4001)
1 MB (27C801)
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128 KB (29F010)
256 KB (29F020)
512 KB (29F040)
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When a single voltage FLASH memory is used,
it can be reprogrammed onboard. Be careful, however,
to not destroy the bootstrap code -
this will result in system's inability to restart.
Additional PROM storage can be provided with extension boards,
using the free chip_select ports.
(Port 0 also can be used, if the socket is keeped empty).
The auxiliary SEEPROM pool
is provided with two soldered 8 KB chips (Microchip 24C65).
It is intended to store system and
application parameters and critical data.
The pool is accessed via I2C serial bus interface,
incorporated in the CPU chip. Therefore, it does not consume
the CPU address space and does not require any chip select ports.
The I2C bus performance is about 100 Kbit/s.
In the write mode, 24C65 SEEPROM provides
a 2 ms write time for a single byte or 8-byte page,
and 1,000,000 write operations are guaranteed.
The Xilinx XC4010E based system controller
contains several separate devices and logical circuits:
- the IP controller,
- the system's interrupt controller,
- the system's powerup/reset and clock logic,
- the logic to control the onboard RS232 driver,
- the chip select logic for onboard DRAM chips,
- the common chip select and address decoding logic.
The system controller uses a single chip select port (port_1):
first, to map the entire IP space to the CPU address space and,
second, to provide access to device control registers for
its internal devices. The port window mapping is the following:
The common chip select and address decoding logic is activated
by the CPU access to the port_1 and defines which Xilinx's internal
device is addressed. It then activates the referenced device.
The port has a 16-bit width to be compatible with the IP bus width,
but the most of device control registers are accessed with 8-bit
bus operations.
The IP controller translates between the two buses,
the GPFC system bus
and the IP bus.
It also delivers IP interrupt requests to
the interrupt controller
for further processing.
The IP controller is activated when the CPU accesses the IP space
(either memory or I/O or ID). It generates an appropriate IP bus
cycle and provides the data transfer directly from bus to bus.
Thus, an IP bus cycle is effectively nested in the system bus cycle.
The data transfer width is 16 bit when accessing the IP memory space
and 16/8 bit for the I/O or ID space access.
The IP controller currently supports the 8 MHz IP bus only.
The DMA mode of operation is not supported, because the system bus
is a single master one.
Also, 32 bit data path is not supported.
IP interrupt processing is performed in the interrupt controller.
The IP controller only translates IP-module's interrupt requests
to appropriate inputs in the interrupt controller.
The interrupt processing procedure does not require to run
an interrupt acknowledge cycle on the IP bus,
since all interrupt attributes are preprogrammed in the
interrupt controller.
This means that IP interrupts are completely decoupled
from the system bus interrupts.
However, the IP controller provides an optional operation
to execute the IP interrupt acknowledge cycle, which returns
an appropriate vector from the addressed IP module.
This operation may be useful with some specifically designed
IP modules (when an interrupt request is deactivated only
by reading the vector).
The main GPFC board has only two IP "slots" but all needed
control signals are provided on the system bus
(and extension connector)
in order to add two more slots located on an extension board.
This will require only IP bus transceivers and IP connectors.
The interrupt controller provides the centralized interrupt processing
for 13 interrupt sources:
- 8 IP interrupts
(from the IP controller),
- ABORT button's interrupt
(from the onboard auxiliary connector),
- 4 "external" interrupts
(from the system bus extension connector or
the onboard auxiliary connector).
All interrupts are to be configured before their use, updating a
table maintained by the interrupt controller.
The table contains an entry for each interrupt source, where IPL
(interrupt processing level) and interrupt vector are written.
Any interrupt source can be associated with any IPL and vector,
thus providing maximum flexibility in configuring interrupts.
The interrupt controller supports a local loop testing of interrupts,
when interrupt requests are generated internally under the program control.
This mode of operation is intended for diagnostic, troubleshooting
and debugging of new hardware.
The following functions are implemented in the Xilinx chip
to minimize the onboard logic circuitry:
- Using signals from the onboard power monitor IC,
a separate "device" performs the system powerup/reset
sequence.
It also processes signals from
the two external sources (SOFT and HARD reset buttons).
Both these inputs are routed to the onboard auxuliary connector.
- One more "device" provides the entire system with clock signals
(32/16/8 MHz) using the onboard clock generator.
- A separate "device" controls the onboard RS232 driver, allowing
to shutdown it under the program or external (button) control.
This device also detects when an alternate (external) driver
is used and automatically disables the onboard one to prevent
the possible conflicts.
- The DRAM address decoding circuit provides chip select signals
for the onboard basic DRAM pool.
Besides, a possibility is provided to use a considerable FPGA space,
still remained free, for additional coprocessor-like devices.
These devices can be accessed via their control registers,
located in the free area of the port_1 address space.
The IP bus, as specified by the VITA-4 document, includes the two sets
of signals: bussed ones (address/data, sync) and non-bussed, which have
to be routed to individual module slots providing
the module selection mechanism.
The GPFC's implementation of the IP bus has the following features:
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The full range of IP operations is supported, including ID, I/O and
memory space access (word and byte modes, accordingly to the VITA spec).
All IP spaces are directly mapped into the CPU address space,
where each IP module has its own
"window".
IP interrupt processing is performed in the
interrupt controller
which provides a flexible interrupt processing policy.
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Limitations (see the
IP controller
description):
- 8 MHz clock is only supported
- 16-bit data path is only supported
- DMA mode is not supported
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Separate bus transceivers drive the local IP bus
(for 2 IP modules) on the main board.
An extension (IP carrier) board will to provide
its own IP bus transceivers.
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IP modules are powered from the carrier board (either the main GPFC
board or an extension board) via the IP bus connector:
+5V (max 3A for 2 modules),
+12V (max 1.5A for 2 modules),
-12V (max 1.5A for 2 modules).
See also under the
"Power distribution"
title.
In addition to the IP bus connector,
the IP specification defines a second connector (of the same type)
for arbitrary use by an IP module. It is intended for connecting the IP module
to the external equipment. The most of commercial IP carrier boards
have an intermediate connector routed to this "external I/O" connector.
The GPFC board design follows this practice.
Two 50-pin headers provide the industry standard "external I/O" connection
for two IP modules:
The GPFC itself does not limit the height dimension of IP modules
(see the VITA-4 specification for details).
However, when embedding the GPFC into the equipment one has to
consider the possible height limitations.
The GPFC power distribution scheme makes use of a stackable power connector.
This scheme enable each GPFC board to be designed independently from others in
the aspect of power consumption.
The power connector provides the following voltages (and max total currents):
- + 5 V (max 6 A)
- +12 V (max 2 A)
- -12 V (max 2 A)
- Ground return current max 10 A
A fuse and filtering capacitor (for each voltage) are installed
at power entry on the main and extension boards.
The GPFC is designed for low power applications.
The goal was to provide its operation without the need in forced air cooling.
The following design solutions contribute to this goal:
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The IC component selection by low power and
effective heat dissipation criteria.
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Placement of the most of IC components on the board side,
which is
opposite to the side, where IP modules are installed.
This distributes main heat sources and also provides
as much as possible of free space between IP modules
and the GPFC board to promote air convection.
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Placement of the most of connectors in a way promoting
air convection
(providing that the board is properly space oriented).
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The GPFC's mode of operation also contributes to the overall low power
consumption:
in each bus cycle the CPU accesses one and only one peripheral,
all others are deselected. Because almost all ICs have a power saving
feature, they are in nearly shutdown state when deselected.
So, only the CPU, Xilinx, system bus transceivers and
a single "averaged" peripheral are seemed
as running continuously.
The CPU has many power saving features,
dynamically controllable by software, including the complete
shutdown of some internal devices when not used.
The most of Xilinx firmwared devices
(including the IP and interrupt controllers)
also sleep most of the time.
Bus transeivers work in the "bus hold" mode.
This minimizes the frequency of bus transitions and, therefore,
the total power consumption,
which, for high speed CMOS ICs, is mostly associated with state switching.
They also convert TTL signal levels, provided by the CPU chip,
to CMOS levels: although the rest of IC components may accept TTL levels,
they all show almost twice lower power consumption values
when driven with CMOS level signals.
Also, the basic DRAM pool is organized in a way
that only one chip is selected
when accessing any DRAM location, while the second one sleeps.
Thus, the total pool consumption is very close to the one
of a single chip.
The basic PROM pool is typically used only at system startup
and keeps nearly shutdown state the rest of the time.
Altogether, this makes the GPFC a really "cold" device.
However, the final decision on avoiding the forced air cooling depends
on IP modules installed.
Also, the surrounding environment and the GPFC board's
space orientation have to be taken into account.
The GPFC is primarily intended for embedded applications.
To facilitate this,
the following features are provided in the design:
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Compact board form factor (3U, 160x100mm).
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The four mounting holes to mount the board
in the hosting equipment.
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Absence of the onboard controls and indicators.
All connections to the external world
are via either IP "external I/O" connectors
or auxiliary connectors (RS232/UARTs, reset buttons,
external interrupt inputs, I/O ports, BDM interface).
All the onboard connectors
(except the IP and interboard extension ones)
are of the same type: 2.54" terminal strips for use with
flat cable assemblies.
This allows to mount the GPFC board on a "meta-carrier" board,
using a direct board-to-board connection
(such solution is used in SEDAC crate controller application).
Moreover, auxiliary connectors, either vertical or right angle,
can be placed at any of the two board sides,
thus enabling different mounting strategies:
Although the basic GPFC configuration is intended to be the minimal
functional subset, it can be somewhat further reduced to eliminate
some components and, accordingly, features:
- Interboard (extension) connector
- Can be omitted when the application requires a single board
GPFC configuration.
- DRAM
- There are 2 DRAM chips on the GPFC main board.
One can solder only one chip, thus reducing the basic
RAM pool to 2 MB
(or even exclude both, if the RAM pool is to be provided on
extension boards).
- SEEPROM
- Again, one can solder 1 or 2 chips (8 or 16 KB, accordingly),
or exclude both.
- RS232 driver (+ dedicated auxiliary connector)
- Can be omitted when the application provides its own (external)
physical media interface, or does not need serial
channels at all.