Aim of this page is to link the different activities on trigger and data acquisition in the framework of the World-Wide Study of Physics and Detectors for Future Linear e+e- Colliders.
An overall description of the R&D program of the World-Wide Study can be found in the Linear Collider Detector R&D paper available as postscript or PDF version. For other activities in the International Linear Collider Detector R&D see this WWW page
The trigger and data acquisition concept for a Linear Collider detector was developed in a series of workshops. All LC detector designs include a "software trigger" as shortly described in the following. Details can be found on the workshop pages and links listed below.
All present LC detector designs are based on a software trigger with the following assumptions :
- dead time free pipeline during a bunch train,
- no hardware trigger,
- frontend pipeline with capacity for storing data from a complete train,
- event selection by software.
Although the DAQ system for the LC detector is more relaxed than for LHC experiments, the frontend readout systems for the high granularity detectors impose demands sometimes beyond those for LHC, both for electronic integration and power consumption. This necessitates R&D for the frontend readout which must be covered by the specific subdetector groups. For the overall event building, proof of concept and the development of event selection strategies will require event-builder prototyping as well.
For the subdetectors the large number of readout channels demand development of high electronic integration and smallest possible power dissipation to reduce cooling needs, reduce dead space for the readout electronics and readout cables at the detector, achieve manageable data rates for the high granularity systems by online zero suppression, hit detection and data processing, and allow online monitoring and calibration of all frontend readout channels.
The only part of the central DAQ system needing hardware R&D is the common interface of the frontend readout systems to the central DAQ system. This common interface has to be specified and designed in close cooperation with the different detector R&D groups in order to ensure a unique interface or at least a small set of standardized interfaces for all subdetectors. The design and layout of a common frontend interface for the central DAQ could already be used in test beams and should be developed in parallel to the frontend designs of the different subdetectors prototypes in order to be ready for test beam operation.